Enhanced active disturbance rejection controller in the unified power quality conditioner for power quality and stability improvement

During national industrialization and urbanization, the power industry has advanced significantly. However, the extensive use of power electronic devices has led to a substantial increase in nonlinear loads in transmission, distribution, and power terminals. This has altered the current and voltage waveforms of the power grid, causing harmonic pollution and affecting its safe and stable operation. With the objective to promote complete power quality management theory and technology, this research focuses on the unified power quality conditioner (UPQC) in low-voltage distribution networks. In order to achieve novel outcomes, the research investigates important technologies such as detection, modulation, topology, modeling, and control. In order to analyze power flow and output voltage and current quality, it first looks at the UPQC structure and creates mathematical models for its series, shunt, and DC sides. Second, it examines the UPQC DC control module's voltage waveform when it is under PI control.The Active Disturbance Rejection Controller (ADRC) and super-twisting sliding mode controllers are intended to take the role of the DC module PI controller in order to lessen oscillation of the DC module output voltage.The compensation properties of UPQC under various controllers, as well as the oscillation of the intermediate DC voltage, are investigated and examined. Finally, this study offers a second- and third-order mixed generalized integrator (MSTOGI) that uses linear active disturbance rejection controller (LADRC) to efficiently reduce the detection delay for fundamental positive sequence components under non-ideal grid voltage settings.The MSTOGI-PLL based on LADRC achieves accurate phase locking under non-ideal grid conditions, ensuring unity power factor and improving waveform quality. Experimental results show that compared to PI-controlled MSTOGI-PLL and traditional Synchronous Reference Frame PLL (SRF-PLL), the LADRC-controlled MSTOGI-PLL significantly reduces the THD of load-side output current (47.5% lower than PI, 61% lower than SRF-PLL) and voltage (14.4% lower than PI, 83% lower than SRF-PLL).