Implementation and simplification of an Output Shifted Coding Modulation (OSCM) on a high speed DSP processor / Roslina Mohamad, Wan Nor Syafizan Wan Muhamad and Rosmalini Abdul Kadir

Forward error correction (FEC) codes are a subclass of error correcting codes, have become an invaluable tool in 'closing' the link budget of wireless-based digital communications systems. The disadvantage of FEC is the tradeoff between error performance and the decoding complexity resides on the choice of the code constraint length. A solution to this problem was provided by Ungerboeck, who presented a technique which is called Trellis Coded Modulation (TCM). However, there is still a trade-off at work; trellis coded modulation achieves coding gain at the expense of decoder complexity. Due to this problem, a new coded modulation which is a combination of forward error correction codes (convolutional and Viterbi codes) and Tt/4-shift DQPSK is discussed in this research. The new coded modulation is called as Output Shifted Coding Modulation (OSCM). This algorithm also shows that by using low constraint length convolutional component codes, it can outperform the convolutional codes using Viterbi decoders with much higher constraint lengths. It is capable of reducing the bandwidth expansion by using Tr/4-shift DQPSK. This is achieved through fine tuning the set of rules for the mapping of coded bits and also with modifying error detection and correction techniques in trellis diagram. The research work continues with the implementation of digital baseband signal processing with OSCM function on Digital Signal Processor (DSP) Kit TMS320C6711. Single DSP chip is used to implement the baseband processing function due to compactness, low-power consumption and flexibility. C6711 is a member of the high performance DSP family from Texas Instruments (TI) that incorporated the real-time kernel known as DSP/BIOS. The design environment is based on Code Composer Studio IDE (Integrated Development Environment) and the DSP functions are simulated on 150MHz clock C6700 DSP simulator.