Electrical analysis of Si3N4 capping layer and SOI technology in Sub-65 Nm CMOS / Syed Muhamad Firdauz Syed Adrus

Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source, shallow trench isolation (STI) has not been fully utilized up to now for circuit performance improvement. In this paper, two methods have been used on 65nm CMOS that combines with detailed placement and active-layer fill insertion to analyze for performance improvement.
First method is to investigate electrical characteristics for 65 nm NMOS by using Si3N4 capping layer for three different layers thickness (30 nm, 60 nm and 100 nm. Second method is using 0.4 pm thickness of Silicon-on-Insulator (SOI) Technology for 65 nm PMOS. The performance of the devices is analyzed by focusing on the electrical characteristics of Id- Vd and Id-Vg curves for both capping layer and SOI technology.
The results shows that, thicker capping layer thickness offer higher stress in CMOS, this improves the acceleration of electron mobility and increases the drive saturation current in NMOS of about 14%. Meanwhile, by implemented SOI technology shows improvement in threshold voltage (with decrement of 8.5%) and drain saturation current (with increment of 4.7%). The fabrication process simulation and electrical characteristic was simulated by using SILVACO TCAD ATHENA and ATLAS simulator.