High level synthesis for parallel scan / Rihana Yusuf, Norsabrina Sihab and Zurita Zulkifli

As digital systems become more complex, they become much harder and expensive to test. One solution to this problem is to add logic to the Integrated Circuit (IC) so that it can be testable. This concept is an important aspect to be considered in early stage of IC design process. This is different from traditional test philosophy, where the testing is carried out after the 1C design has been completed. In this paper, the scan- based architecture which is widely used in modern design for testing purpose will be employed in testing the IC circuit. However, the applicability of scan testing is being severely challenged recently by four problems which are area overhead, test application time, power consumption, and test-related yield loss. This project addresses the issue of reducing test application time using a parallel scan method in which the test vector has parallel loading and unloading sequence mechanism that can shorten the test application time. A 2-bit Full Adder circuit is utilized as a Circuit Under Test (CUT) while the VHSIC Hardware Description Language (VHDL) is used as a tool to design the whole system and will be run on MAX+plus II platform.