Designing a digital clock using VHDL / Badrulhisham Baharain

This project paper presents the designing a digital clock using VHDL. The VHDL modelling used are behavioural, structural and register transfer language (RTL) modelling. By using this technique it shortens the design process and produced more efficient and effective circuit. The development of digital clock consists of oscillator, multiplexing block, second, minute, hour, cathode converter and decoder. The result is shown by timing diagram.