Design a comparator of 8 bit analogue to digital converter (ADC) in a 0.35 micro meter CMOS technology by using mentor graphics / Tengku Zairi Ezwa Tuan Zakaria

This thesis present the design of a high performance on-chip comparator of 8-bit Analogue-To-Digital Converter (ADC) has been designed in a 0.35µm Complementary Metal Oxide Semiconductor (CMOS) Technology process. Full custom design flow is implemented in which the design starts with schematic entry followed by simulation for characterization purpose and validation. The IC layout of the comparator is achieved along with the post layout simulation and layout verification. The designed comparator is tested in an 8-bit ADC by simulation to determine the functionality and performance. The comparator can handle positive and negative input signals. A polarity signal changes the polarity of the threshold level and makes the output signal always active high. The design is based on basic comparator architecture which consists of three stage; preamplifier, positive feedback decision circuit and output buffer. This architecture provides both good gain and offset characteristics by combining the pre-amplifier and the positive feedback decision circuit. The MOSFETs’ W/L factor of the comparator circuit also contributes to the characteristics improvement. Increment of the pre-amplifier’s input MOSFETs widths increases the gain of the comparator while the width of MOSFETs in decision circuit will determine the offset of the comparator.