Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi

This paper present an analysis and design of Sample and Hold (SH) circuit for front end block pipelined ADC using 0.18um CMOS technology. The objective of this project is to design a sample and hold circuit and analyzing in term of low power and high speed with two different topologies, which are two stage operational amplifier and folded cascode operational amplifier. The analysis of op amp parameters is done for 0.18um CMOS technology. SILVACO EDA tools have been used for schematic design and simulation. Complete Sample and Hold circuit has been designed with 1.8V Vpp, 1.8V voltage supply and 5Mz sampling frequency. The power consumption for two stage operational amplifiers is 0.08 lmW and for folded cascode operational amplifier is 0.593mW. The propagation delay of the circuit is 131.15ns for two stage operational amplifier and 2.7402ns for folded cascode operational amplifier. Based on the analysis and design, two stage operational amplifier can give low power consumption and low speed while folded cascode operational amplifier can give high power consumption but high speed.