Row decoder and row driver custom design using 0.18 um CMOS technology / Md Aizuddin Rosdan

This paper presents a design and analysis of row decoder and row driver used for 2KB content addressable SRAM memory. The decoder and driver were designed in a custom analog design and layout using EDA Tools Software with 180 nm technology Iibrary. The designed was focusing on optimizing the propagation delay and power consumption or dissipation because it is important to achieved fast SRAM transfer data with low power consumption. The row decoder and row driver was designed for 4-16 decoder using Pseudo NMOS. The finding reveals the improvement in propagation delay and power consumption or dissipation. From the finding, the propagation delay speed had improved by 21 ns to 6.18 ns and power dissipation had reduced from 600 mW to 177.54 u.s. The simulation results was referred to the FairChild Semiconductor MM74HC154 datasheet for comparison. The power consumption for the decoder design using Pseudo NMOS also reduced compare to the NAND gate structure. The layout of overall designed have shown the layout versus schematic (LVS) results is equivalent and no error in design rule check (DRC).