Investigation of stress effect technology on electrical characteristics of 90nm CMOS devices / Hanim Hussin, Ahmad Sabirin Zoolfakar and Rosmalini Ab Kadir

The implementation of this research is to find a solution for CMOS devices problems related to hot carrier effect due to advanced technology node where the devices are scaled in nano-region. Stress effect or known as strained silicon technology is capable to increase performance of CMOS devices in terms of the mobility of electrons and holes. This can significantly increased the performance of integrated circuits whereby CMOS devices are widely used. Four fabrication methods are identified for the purpose of this research which consist of shallow trench isolation, silicide, silicon nitride capping layer and embedded silicon germanium effect. All this fabrication techniques will be implemented in simulation using SIL V ACO TCAD tool. The CMOS devices under study will be 90nm CMOS devices. The results will be in the formed of device structure from fabrication process and characterization of the stressed CMOS devices.