Design and analysis operational amplifier using VLSI software / Nordiana Mukahar and Shamian Zainal

This paper describes the design procedure of two stage op amp and folded cascade op amp using VLSI software. Designing high-performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages and low power consumptions but there is trade off among other performances parameter. The appropriate topology among various possible alternatives architecture of operational amplifier is selected in order to achieve higher performance for a desired application. By setting the target specification of the desired performance parameter, the value of the power supply voltage and the bias current can be determined. It start by defined the topology of the operational amplifier circuit that consist of three stage; differential amplifier, common source and output buffer. The folded cascade is then implemented to the circuit to improve the performance. The folded op amp feature high bandwidth, low supply voltage and low power dissipation. The op amps have been designed with a standard 2μm CMOS technology by using Tanner Tool. Measurement shows the unit gain bandwidth of folded op amp is 5 MHz for a 12 pF load and the amplification is 93 dB, while drawing 20 μA for 2.5 V power supply. It shows that the dc gain of folded op amp is 14 dB higher than two stage op amp and the bandwidth also 5 times larger than 2 stage op amp. The folded op amp can swing up output voltage 99% close to power supply.