Study on the effect of short gate length on 65nm NMOS transistor using SILVACO TCAD / Azira Ahmad Tarmizi

The aim of this work is to design and study on the effect of short gate length of 65nm NMOS transistor using SILVACO TCAD. A 65nm NMOS was designed and fabricated to study its electrical characteristics. To simulate the electrical performances of the 65nm NMOS, ATHENA and ATLAS of SILVACO TCAD tools were used. Downscaling of NMOS transistors will change its operational characteristics. A shorter gate length will lead to Short Channel Effect (SCE) to arise which are channel length modulation and Drain Induced Barrier Lowering (DIBL). The Short Channel Effect can be observed from the comparison of the simulation result of the long gate length (0.3 pm) and short gate length (65nm). Based on the result, SCE which are channel length modulation and DIBL can be observed from the short gate length (65nm) NMOS transistor. The results showed that inclusion of Halo implantation has reduced the DIBL effect as the ID plot showed that when ID= 0 and VTH= 1.87 V. In addition, retrograde well doping reduced the channel length modulation since ID increase by a factor of 1.3 which is lower compared to ID for 65nm conventional NMOS increase by a factor of 1.6. Lastly, the Halo implantation and retrograde well have been proven to reduce the channel length modulation as well as DIBL effect shown by the findings and supported by other studies.