High speed 4-bit flash ADC with low INL and DNL using 0.18µm CMOS technology: article

The purpose of this paper is to design a High Speed 4 bit Flash Analog to Digital Converter (ADC) with low Integral Non-Linearity (INL) and Differential Non-Linearity (DNL). A high speed Flash ADC is obtained by selecting the best topology for the comparator and encoder design. In this paper, the best topology used for the analogue side is the open-loop comparator replacing the conventional comparator. However, some modification is made on the comparator which is by adding hysteresis circuit. The purpose is to lower the non-linearity effect on the output of the ADC. Meanwhile, for the digital side, the best topology used to design the flash ADC is the XOR encoder. The technology used to design this ADC is 0.18µm CMOS technology. The software that is used to design this Flash ADC is Silvaco Electronic Design Automation (EDA) Tools. This includes schematic-drawings, simulations, layout-designs, and overall checking of the circuit. Summarizing the simulation results includes a lower delay comparator design which is 0.2569ns at maximum sampling frequency of 500MHz with analogue input of 1.8V. The simulation of the XOR encoder shows that the topology has the lowest power consumption which is 1.5343mW with a propagation delay of 25.4890ns. The overall DNL for this flash ADC ranging from -0.4LSB ~ 0.3LSB and the INL ranging from 0.6LSB ~ 0.4LSB. Simulation also shows an ADC power consumption of 38.8072mW and a propagation delay of 58.44ns for a 1.8V supply.