Optimization of gate dielectric thickness in PMOS structure using silvaco TCD tools

The dielectric layer in Metal Oxide Semiconductor Field Effect transistor (MOSFET) is a layer of very thin oxide which serves as insulator between the gate and channel. It’s also known as gate oxide or gate dielectric. This paper presents the effects of gate oxide thickness on p-channel MOSFET (PMOS) performance by optimizing the gate oxide thickness using Silvaco Technology Computer Aided Design (TCAD) software. The gate oxide thickness was found directly proportional to the threshold voltage. By using Silvaco TCAD, the optimum value obtained for gate oxide thickness is 3 nm. In the oxidation process the oxidation time is the best optimizer parameter compared to pressure and temperature. The optimum amount of HCl in oxidation process is 3%.