Logical effort using particle swarm optimization algorithm - an examination on the 8-stage full adder circuit

In semiconductor manufacturing, the fabrication cost of integrated circuits (I.C's) are associated with the development time and the materials used (chip area), where it can affect the speed and power requirements. Before choosing the best design, the goodness of each option, especially regarding the speed and power consumption must be determined. The speed and power consumption in the digital circuits depends on the gate sizing of that circuit which means that the best gate sizing will give the efficient speed and the low power consumption to that circuit. The method of Logical Effort (LE) has recently been introduced to allow for both quick and accurate analysis of Complementary Metal Oxide Semiconductor (CMOS) circuits. But, the limitation of the LE method (such as time spent to calculate the delay and also try and error method to find the specific delay) must be avoided to reduce the cost. By applying Particle Swarm Optimization (PSO) method, the LE problem for electronic circuits is solved automatically, to find the gate sizing within a short period of time. The best gate sizing that will be determined will give the required delay, where it is the best choice for certain applications such as in embedded computers.