A low power 0.18µm CMOS technology integrating dual-slope analog-to digital converter: article

In this paper, a 4-bit integrating dual slope analog-to digital converter (DS-ADC) is designed which consumes low power and simplicity but slow conversion time utilizing a Silvaco Electronic Design Automation (SEDA) tools with an advanced 0.18µm CMOS Technology using 1.8V power supply. This ADC contains three main components of integrator, comparator and control logic at which the integrator is realized with a two-stage operational amplifier (op-amp) that provides sufficient gain, ICMR and power dissipation. Simulation confirms that the proposed ADC architecture shows a power efficiency of 2.47392mW.