Design a single stage folded cascode amplifier with gain booster for sample and hold stage of pipelined ADC

This thesis presents the full custom design of an operational transconductance amplifier (OTA) for the sample and hold (SHA) stage of a 10-bit 50-MS/s pipelined analog-to-digital converter (ADC) implemented in a MIMOS 0.35um Complementary Metal Oxide Semiconductor (CMOS) process. Full custom design is implemented in which the design start by determining the specification followed by netlist entry. The simulation is done to verify the specification purpose. The layout of the OTA is constructed after all the parameters are finalized. The last stage of the full custom design is post layout simulation to see the effect of parasitic capacitances to the performance of the design.