Simulation of 65nm vertical double gate NMOS using Silvaco TCAD tools: article / Mohd Ridzuan Mohd Nayin @ Mohd Nayan

This paper has demonstrated structure design and simulating electrical characteristic of Vertical Double Gate nchannel MOSFET (NMOS) using Silvaco TCAD Tools. Objectives of this study are to design 65nm Vertical NMOS, meet the specification provided by International Technology Roadmap Semiconductor (ITRS) and to study the effect threshold voltage by varying body channel doping and oxide thickness. The investigation of Vertical NMOS characteristic is done through structure design and simulation electrical characteristic using ATLAS tools Silvaco. The extracted values are compared to the ITRS specification. At gate length, Lg=65nm, channel body doping concentration of 1.5×1018 cm-3 and oxide thickness, Tox=2.2 nm, this design have a drive current of 450µA/µm, low off-state leakage at 18.14nA/µm and subthreshold swing, SubVt of 76mV/decade. From Id versus Vgs characteristic curve, threshold voltage is 0.19V at Vds=0.1V.