Study of 4-bit pipeline flash analog to digital converter using 0.18µm CMOS technology / Norhafizi Ishak

In this paper, effect of pipelining in 4 bit flash ADC is investigated. By adding latch staging in decoder circuit, it can improve the accuracy and meta-stability error of output signal of the flash ADC. Two stages comparator that has high speed, high level accuracy and non-compensation is used. The output of comparator is generated in form of thermometer code will be converted to binary code in decoder stage. Effect of load capacitor to the comparator stage also will be analyzed. Small value of capacitor will lead to short time transition of state, mostly because of charge and discharge of the capacitor. LTSPICE is used to design the circuit and simulate the flash ADC circuit to produce waveform of flash ADC. Based on the waveform generated, the meta-stability error of the output waveform will be analyzed. The proposed pipeline flash ADC will produce less meta-stability error than conventional flash ADC. The binary code of the conversion of input analog signal also will be analyze and tabulate.