NMOS gate length scaling for 0.13µm using silvaco TCAD tools / Azlinawati Mohd Husain

This project is about down sizing the size of gate length of NMOS (n-channel MOSFET). The NMOS gate length is reduced from 0. I 8µm to 0. I 3µm. In order to reduce the size, the design process is based on the scaling factor rules. This process is done by using appropriate doping profile and oxide thickness according to the channel length in order to improve the device performance. This process is design for 0.13µm NMOS transistor with L_gate = 0.131 µm and L_eff = 0.00765µm. The threshold voltage, VT obtained was -0.1 V and the drain current of I07µA⁄µm was obtained at V_D=V_G =2.5V. The design device is characterized for on-state and off-state performance. Electrical parameter extraction is done to develop this process which can be used in future circuit designs. Silvaco TCAD Tools is used to simulate the process and analyze the electrical characteristics curve of the scaled NMOS. The study is about the results that will indicate the characteristics and effects of the reduction of gate length that brings to the impact of devices. The design process and design simulation is carried out using Silvaco's simulator tools Athena and Atlas.