Translation buffer design project

Translation buffers are used in common everyday applications to convert properties of different logic types to be compatible with other logic types. This project is to design a translation buffer using the CMOS process that allows a 100K ECL logic block to drive 1.5 CMOS chip. A common design tool Pspice was used to analyze the buffer to produce the required specification. The design translation buffer will be used to fit the schematic below containing the driver ECL and load CMOS.