5-bit wallace-tree thermometer-to-binary encoders 0.18um CMOS technology for flash ADCs comparing conventional CMOS and transmission gate CMOS full adder / Alia Aqilah Ahmad Termidhi

The thermometer-to-binary decoder becomes the constraint of the ultra-high speed CMOS flash analog-to-digital. This paper present two different types of 5-bit Wallace-tree thermometer-to-binary encoders for ultra-high speed in flash ADC in 1.8V, 0.18µm CMOS technology. Two different types of Wallace-tree encoders are compared using different full adder which are Conventional CMOS full adder and Transmission Gate CMOS full adder. The study was carried out on these two types Wallace-tree thermometer-to-binary encoders in term of its parameters, namely power consumption, number of transistors, and delay. In this project, the simulation results are generated using SILVACO EDA tool. Gateway Silvaco EDA tool is used in the design and the schematic simulation. Layout and verification of the design was verified using Expert SILVACO EDA tool. The results showed that the proposed study produces better performance in power consumption over the previous work. The power consumption for the encoder using Conventional CMOS full adder reads 4.27403e-004W while for the Transmission gate CMOS full adder reads 6.82652e004W. In addition, according to the results, encoder using Conventional CMOS full adder can be concluded to be a suitable full adder to be used in Wallace tree thermometer-to-binary encoder for efficient flash ADC designs based on power consumption, number of transistors used and delay. Encoder using Conventional CMOS full adder consume 4.27403e-004W power consumption and 360.7ps delay but requires 616 number of transistors.