Design of SAR ADC control logic using verilog HDL

This paper presents the design of successive approximation register analog to digital converter (SAR ADC) control logic using Verilog Hardware. Description Language (Verilog HDL) coding. This control logic design methodology is based on Xilinx ISE 8.1 i Field Programmable Gate Array (FPGA) design flow from design entry until implementation process. The behavioral coding of SAR ADC control logic was written in Veri1og HDL design entry by using Finite Sate Machine (FSM). It was synthesis to get the schematic, check syntax and we can be known the maximum of the clock that can be used. This 10-bit SAR ADC control logic was designed to operate at frequency of 33.3 MHz and the sampling rate is 3.33MSample/s. It was simulated by using Mode]sim IJ1 6. 0d simulator. The SAR ADC control logic produces 10-bit at 33.3 MHz system clock and the power consumption is l8mW. For the implementation process level place and route is used to generate the floor-planning of the SAR ADC control logic on FPGA This project has been successfully and for the future, this project can be improved.