Simulation of drain induced barrier lowering (DIBL) in metal oxide semiconductor field effect transistor (MOSFET)

This paper shows Simulation of Drain Induced Barrier Lowering (DIBL) in Metal Oxide Semiconductor Field Effect Transistor (MOSFET)”. The research and study on this is investigated. Using software from SILVACO International, the simulation of the N-channel metal oxide semiconductor (NMOS) can be studied and the study is about DIBL due to short channel. SILVACO technology computer-aided design (TCAD) software is use to do the simulation and to obtain all the results needed. The virtually fabrication of NMOS is done using ATHENA module meanwhile for electrical characterizations of NMOS is done using ATLAS module. Using this software, the structure of MOSFET and I-V curve can be plotted through the TONYPLOT. In this study, the drain voltage, VD and channel length, L act as the main roles in the results. Therefore, to see the role of drain voltage on DIBL, five different values of drain voltage, VD which are 0.1 V, 0.2 V, 0.3 V, 0.4 V and 0.5 V are used. Meanwhile, for channel length, L, the values used are 0.20 µm, 0.30 µm, 0.40 µm and 0.50 µm. From drain current, ID versus gate voltage, VG (I-V) curve, the value of DIBL is obtained and analyzed to complete the analysis of DIBL. When the drain voltage, VD increasing, the potential barrier in the channel decreasing which leads to DIBL. As the voltage drain, VD is increasing, and the barrier height is decreasing while the drain current, ID is increasing. This project do achieved the objectives of the project.