Design of 8T SRAM and sense amplifier using 0.18µm CMOS technology / Rozita Muhammad

In this work, an 8T SRAM operation and sense amplifier will be designed for 0.18µm CMOS technology. The operation of SRAM is to retain data content as long as electric power is supplied to the memory devices, and do not process for rewrite or refresh data. Also, the SRAM cell is preferred because of its low power operation. The performance of SRAM is measured by its static noise margin - a measure of the cell’s stability to retain it’s the data state. While for the sense amplifier, it is used to translate small differential voltage to a full logic signal that can be further used digital logic. The choice and design of a sense amplifier in this work will define the robustness of bit line sensing, so it will impact the read speed and power.