Analysis and optimization of 3 to 5 GHz CMOS low noise amplifier for ultra-wideband system: article / Khairul Anuar Abdullah

This paper presented analysis for a single stage Ultra-wideband CMOS Low Noise Amplifier interfacing interstage matching inductor cascade inductive source degeneration. Cadence design tool is used to optimize the simulation performance base on transistor size and inductor. The LNA is implemented using Siltera 0.18µm CMOStechnology for a 3 to 5 GHz ultra-wideband system. By carefully optimization, size of transistor CMOS and an interstage inductor can increase the overall broadband gain while maintaining a low level of noise figure of an amplifier. The optimization of the LNA UWB has stability factor’s more than 1, power gain +11.27dB and noise figure of 2.15 dB at frequency 4.5GHz.