Power efficient 64-BIT dynamic comparator using 0.18um technology: article / Mohd Khushairi Mohd Zaidi

This paper presents the comparative study on 64-bit dynamic comparator using different technology. The objective of the paper is to study and compare the speed of the comparator and to compare the power consumption for comparator in 0.5μm and 0.18μm technology. Comparator is a device that compares two inputs and chooses the high/low or same value to be the output. The tools used in designing comparator are SILVACO GATEWAY for schematic design. Result show that the power consumption is and the delay is 3.81nW and the delay is 142.98ps.