Design a comparator of 8 bit analogue-to-digital converter (ADC) in a 0.35 micro meter CMOS technology by using mentor graphics: article / Tengku Zairi Ezwa Tuan Zakaria

A high performance on-chip comparator of 8-bit Analogue-To-Digital Converter (ADC) has been designed in a 0.35µm Complementary Metal Oxide Semiconductor (CMOS) Technology process. Full custom design flow is implemented in which the design starts with schematic entry followed by simulation for characterization purpose and validation. The IC layout of the comparator is achieved along with the post layout simulation and layout verification. The designed comparator is tested in an 8-bit ADC by simulation to determine the functionality and performance. The comparator can handle positive and negative input signals. A polarity signal changes the polarity of the threshold level and makes the output signal always active high. The design is based on basic comparator architecture which consists of three stage; pre-amp, decision circuit and output buffer. The results that were obtained through these simulations showed that comparator design achieved power consumption of 958.69µW, with supply voltage of 5V. Further research on the MOSFETs W/L factor has successfully improved the characteristics of the comparator to perform for the offset of 620µV. The uses of a latch as the positive feedback decision circuit and the improvement in offset have contributed to the speed performance of the comparator to achieve propagation delay of 3.52ns.