High speed and low power double tail comparator for ADC application using 0.13um technology: article / Nur Fauzana Taib

This project proposes design Double – Tail Comparator for analog to digital converters (ADCs) application. This design gives better performance of the comparator by minimizing the propagation delay and the power consumption. The schematic design for this proposed design is obtained using 0.13 μm technology with supply voltage of 1.8 V and the operating frequency of 800 MHz. The design is carried out using Mentor Graphics tools and Silterra 0.13 μm technology files. The schematic design and simulations is performed using Mentor Graphics Design Architect tool. At the end of this project, the proposed design results to reduce the propagation delay and the power consume for the comparator circuit which is very important issues for various applications in electronics design.