Analysis of pipeline ADC performances with different sample and hold circuits: article / Asma Mohd Salleh

s paper present the analysis of pipeline analog-todigital converter (ADC) with different architecture of sample and hold circuits. We focused on the comparison of the 1-bit pipeline ADC performances in term of speed and power using double buffer and double sampling sample and hold (S/H) architectures. S/H circuit is the most power hungry block that plays a crucial role in pipeline ADC. An appropriate and precise S//H circuit is needed in order to optimize the power dissipation of pipeline ADC without affecting its performances. This pipeline ADC was designed and implemented using CMOS 0.18pm technology with 1.8V supply voltage in Silvaco EDA tool. Double sampling S/H is suitable for pipeline ADC since it consume less power and faster than double buffer S/H at low clock period.