Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi

This thesis presents the comparative study on 64-bit dynamic comparator using 0.18μm CMOS technology. The objective of this thesis is to study and compare the speed of the comparator using 0.5μm and 0.18μm technology and to compare the power consumption/dissipation for comparator in 0.5μm and 0.18μm technology. Comparator is a device that compares two inputs and chooses the high/low or same value to be the output depends on the device application. The tools used in designing comparator are SILVACO GATEWAY for schematic design. Result show that the power consumption are 3.81nW and the delay is 142.98ps.