Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi

Mohd Zaidi, Mohd Khushairi (2013) Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi. Degree thesis, Universiti Teknologi MARA (UiTM).

Abstract

This thesis presents the comparative study on 64-bit dynamic comparator using 0.18μm CMOS technology. The objective of this thesis is to study and compare the speed of the comparator using 0.5μm and 0.18μm technology and to compare the power consumption/dissipation for comparator in 0.5μm and 0.18μm technology. Comparator is a device that compares two inputs and chooses the high/low or same value to be the output depends on the device application. The tools used in designing comparator are SILVACO GATEWAY for schematic design. Result show that the power consumption are 3.81nW and the delay is 142.98ps.

Metadata

Item Type: Thesis (Degree)
Creators:
Creators
Email / ID Num.
Mohd Zaidi, Mohd Khushairi
UNSPECIFIED
Contributors:
Contribution
Name
Email / ID Num.
Thesis advisor
Hassan, Lailatul
UNSPECIFIED
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering > Applications of electric power
Divisions: Universiti Teknologi MARA, Shah Alam > Faculty of Electrical Engineering
Programme: Bachelor of Electrical Engineering (Hons) in Electronic
Keywords: Power consumption, comparator, power dissipation
Date: 2013
URI: https://ir.uitm.edu.my/id/eprint/102889
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