Comparative study of conventional and modified level shifter in 0.18um technology / Jared Anak Jahari

A comparative study of conventional and modified level shifter in 0.18um CMOS technology have been presented. The objective of this paper is to study its power consumption. Another objective of this paper is to study the speed of the both conventional and modified level shifter. The level shifters that have been used are conventional type-I and contention mitigated. These two types of level shifter have been improved by varying the reverse body bias from 0.1V, 0.3V and 0.5V. Circuits have been simulated in Silvaco EDA with 0.18um CMOS technology. Modified conventional type I level shifter shows power consumption of 4.8409pW while conventional type I shows power consumption of 3.4163pW. Besides that, contention mitigated level shifter show maximum power consumption of 3.9010pW as compared to 5.2083pW of modified contention mitigated. From the simulation results, the design circuit able to shift down the voltage from 1.6V with slightly increase of power consumption with better speed.