Comparative study on different type of multiplier in verilog HDL / Nik Ahmad Afnan Nik Azman

This thesis presents the comparative study on different type of multiplier in Verilog HDL (Hardware Description Language). Multiplier is one of the most important components in digital design system and embedded applications. This research study on the different type of multiplier on the algorithm, implementation on Verilog and performance analysis. Today researches already creates so many type of multiplier. This paper helps by doing comparative study of some of this multiplier for future reference. Three type of multiplier used in this comparative study, that are Array, Vedic and Wallace with variation of 4-bits and 8-bits. This technical paper deals with design, synthesis and simulation using Quartus Prime 17.0 Lite Edition and Modelsim 10.5b. The performance of the multipliers is based on the report power and area. Quartus Prime 17.0 Lite Edition used to check the wire connectivity in logic and module of the design using RTL (Resistor-Transistor logic) circuit. To check the validity and functionality of the multiplier, Modelsim 10.5b software are used. The same input data is used on each multiplier because it is expected to get the same output. In this study, it shows that the performance of multiplier are depending on it algorithm. The algorithm of multiplier help the design become more better in performance of power and area when the number of bits changed.