Implementation of memristor using 0.13^m technology in NAND & NOR for hybrid CMOS integrated / Nurfadzilah Fathin Sharin

This thesis describes the the use of nanoelectronic device known as memristor as an alternative device structure to CMOS in forming digital logic gates. The purpose of this research project is to develop a new model parameter based on actual measured data with all parameter described from the fabrication data. The I-V characteristic of the fabricated memristor is studied to form a Spice Macro model to represent the memristor and implemented into NAND and NOR gate. The NAND and NOR logical circuit will be designed and it will be simulated using LTspice software and producing designated layout using 0.13p,m of Silterra technology in Mentor Graphic software and it will be compared with an existing spice model. The Hybrid CMOS NAND circuit designed, in comparison to conventional CMOS NAND using the Spice Macro model, is 68.90% times smaller and 47.90% times lower power consumption while the Hybrid CMOS NOR is 71.82% times smaller and 82.13% times lower power consumption than conventional CMOS NOR. This device will be beneficial to the technology as it is smaller with a high density and faster with low power consumption compared with the CMOS NAND and NOR.