Simulation of Planar and Finfet Transistor Model for Digital Gate Applications / Siti Aishah Abu Salim

In this work, FinFET (dual-gate) transistor is simulated using computer added design (CAD) tools to replace the conventional planar MOSFET. Nowadays planar transistors are no longer clean due to current leakage during on-off switches. Thus, these effects have caused some heat and power issues. FinFET transistors offer superior performance as the device is scaled into the nanometer. Therefore, the ON current was investigated by analyzing the I-V characteristic. Also the gate sizing was investigated and the results have shown the differences in their performances. In addition, the SPICE models of 32 nm were employed for inverter, NAND and NOR gates and the results were verified by DC and AC analysis. The results indicate that FinFET circuits have better performance and produced less leakage when compared to planar MOSFET.