A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar

An iterative mincut heunstic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network. In practice, only a very small number of passes are typicaUy needed. To deal with cells of various size , the algorithm progresses by moving one cell at a time between the blocks of the partition while maintaining a desired based on the size of the blocks rather than the number of cells per block. The program is being develop using this algorithm. The evaluation and comparison also been carried out between this method and Kernighan-Lin method.