Abstract
The term 'Very Large Scale Integration' (VLSI) reflects the capabiiities to integrated thousands of transistors in a single silicon chip. As we all know in this computerised era, VLSI becoming very important. Speed, complexity and sizing are the 3 main targets when designing a single chip using VLSI physical design today. There are several techniques to achieve these targets such as partitioning, placement and floorplanning. Here in my project I only discussed about partitioning because this technique itself has a very wide scope. Here I implement Kernighan-Lin Algonthm and make some improvements to it using size and cut sets weighting. The program is being develop using this algonthm. The evaruation and comparison also been carried out between this method and Fiduccia-Mattheyses method.
Metadata
Item Type: | Thesis (Degree) |
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Creators: | Creators Email / ID Num. Abdul Aziz, Azharul Hisham UNSPECIFIED |
Programme: | Bachelor in Electrical Engineering (Hons.) |
Date: | 1997 |
URI: | https://ir.uitm.edu.my/id/eprint/101305 |
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