A study on optimal layout of CMOS functional arrays / Azhari Mohd. Ali

The objective of this project is to build Optimal Layout of CMOS Functional Arrays 1C standard cell design. Firstly, this topic is discuss about the Optimal Layout of CMOS Functional Array. Optimal Layout is the layout of the arrangement of CMOS transistor with the implementation of a random logic function on an array of CMOS transistor. After discussing about the introduction i.e. the basic of CMOS transistor, we will discuss how to create the Optimal Layout of CMOS Functional Array with the minimum separation based on euler path method.