CMOS low noice operational amplifier design / Saiful Izuan Ramli

This project is to design a low noise CMOS operational amplifier following on given specification such as Vdd equal to+2.5V, Vss equal -2.5V, capacitance load equal to 5pF, and PMOS input differential amplifier. Some calculations have been done to determine the W/L of the CMOS transistor to obtain the result of the specifications based on generic 0.25p technology. The noise of the two different topology circuits is compared to prove the low noise result. CAD tools are used to simulate and verify the design. Finally, the schematic and the layout of the CMOS low noise op amp are obtained.