99.99 second stop-clock / Mohammad Norpaizal Che Pa and Nor Azila Mat Hassan

The circuit uses easily available components. The 1C 4033used in the circuit has a built- in decade counter and 7-segment decoder and driver, making the circuit compact and easy to assemble, due to low component count. The clock signal of 100 Hz, to drive the counters, is obtained from IC 4060 (IC5).
Start/stop executed by a simple flip-flop constructed around IC 4001 (IC6), having quad NOR gates. When start switch (S2) is momentarily pressed, two things happen. One, the counters are reset to zero and second, the counters are enabled to accept the clock signals.
The output of gate G2 goes low; enabling clock signals from IC5 to be accepted by counters IC1 to IC4. Simultaneously, output of gate G1 goes high and capacitor C2 starts charging through resistor R32. During this period this period, pin 8 of gateG3 is low and pin 9 is also low due to high input of gate G4. Hence, the output of G3 is high, resetting IC1 to IC4. After a while, when capacitor C2 has fully charged and pin 8 of gate G3 goes high, the output of G3 swings low, enabling the counter to start counting from 0.00 onwards.
When the stop switch is pressed momentarily the output of gate G2 goes high, disabling the counters to accept the clock pulses. Simultaneously, output of G1 goes low, and capacitor C2 discharges. But as output of G3 continues to remain low, the display is frozen until the start switch is pressed again.