An FPGA implementation of exp-bet scheduling algorithm in LTE networks / Yusmardiah Yusuf

Scheduling mechanism is the process of dynamically allocating radio resources (time and frequency) to User Equipment (UE) that transmits different flows at the same time. It is performed by the scheduling algorithm implemented in the Long Term Evolution (LTE) base station, Evolved Node B. Since the implementation of scheduling algorithm is an open issue in LTE, many packet scheduling algorithms have been proposed by researchers. For instance, various scheduling algorithms which offer several techniques in handling resources to the users have been developed such as Modified Largest Weighted Delay First (MLWDF), Proportional Fairness (PF) and Maximum Rate. This thesis investigates the implementation of the Exponential and Blind Equal Throughput (EXP-BET) scheduling algorithm on the FPGA platform. MATLAB Simulink and System Generator are the tools used for the prototyping. The design using Simulink and System generator can greatly reduce the process cycle from the algorithm to hardware. The metric equation of the EXP-BET algorithm is modelled and simulated using the MATLAB Simulink environment and System Generator tool provided by Xilinx. This design has utilized only 10% of available resources on Virtex-6 device. Then, it is tested on the FPGA using the properties of hardware co-simulation method. The system verification is performed by simulating the hardware co-simulation for the metric value of the EXP-BET metric algorithm and compared against the manual calculation.