Optimization of dc and rf performances using multiple-gated high electron mobility transistor (HEMT) / Mohd Nizam Osman

This study carried out a detail analysis of the perform anc e of HEMT device with various numb ers of gate finger s with respect to their DC and RF performances. The dev ices were fabrica ted by a Plessey found ry which adapted a HEMT process with 0.2 um GaAs technology. A few stages were tak en durin g thi s study to obtain the des ired per form ance for eac h device layout. Th e first was to perform device simulation of different layout s in order to get a preliminary resul t. This simulation result was used as a refere nce durin g the seco nd stage which consis ted of actual dev ice measurement. The measurement was don e using on-wa fer measurem ent technique within the frequency range from 100 MHz to 40 GHz. The result s from these app roaches have show n that each device layout exhibited its own charac te ristics with spec ific adva ntages and disad vant ages toward s the DC and RF performances . The device with higher numb er of gate fingers has superior adva ntages in output current perform ance but exhibited lower cut-off frequency and higher noise compared to the other layout s used in thi s study. The analysis gave some indica tio ns on the wea knesses of a devic e with higher gate numb ers in high frequency circuit design applica tions. Neve rthe less, further research work may also be don e espec ially when invol ving various materi al struc tures, layout typ es and foundry processes in a HEMT device developm ent.