Optimization and modeling of Si₁-ₓGeₓ-FinFET structure based on ratio x, channel dimensions and working temperature

The ever-decreasing size of transistors, driven by the Moore Law, has caused serious heat dissipation problems and increased power consumption at the nanoscale. Fin-shaped Field-Effect Transistors (FinFETs) have become an attractive choice since they can be more easily controlled electrically, reduce leakage currents, and be manufactured using existing techniques. At the same time, the classic Complementary Metal-Oxide-Semiconductor (CMOS) technology is nearing its physical limits. Nonetheless, there is a significant concern that can impact the device's accuracy and efficiency, including thermal problems such as self-heating due to low thermal conductivity and a limited device design. In response to these difficulties, this study is designed to evaluate the thermal and electrical characteristics of FinFET transistors developed from silicon-germanium alloys (Si₁₋ₓGeₓ). Specifically, the work investigates how variations in channel length affect the device's response to thermal stress while keeping channel width and oxide thickness fixed. Si-Ge offers promising opportunities to improve thermal sensitivity in nanoscale transistors, due to its ability to form complete solid solutions across the entire composition range and its notable suppression of thermal conductivity. The molar chemical ratios of Si and Ge (such as Si₀.₇₅/Ge₀.25 and Si₀.₂₅/Ge₀.₇₅) are evaluated to determine performance metrics and determine approaches to improve thermal response as a result of material modification. The MuGFET tool was used to run the simulations at temperatures between 275 and 350 Kelvin. The oxide layer thickness was set to 1 nm, and the channel lengths were 10, 20, and 30 nm. The model included a metal-semiconductor diode junction to improve the accuracy of thermal and electrical predictions. The final results revealed that the ratio (x = 0.5) Si₀.₅/Ge₀.₅ yielded good performance, a more balanced state, and improved electrical properties across all tested ratios. In particular, for channel lengths of 20 and 30 nm, these structures and configurations achieved ideal values for both subthreshold slope (SS = 93.65 and 75 mV/decade), drain-induced barrier lowering (DIBL = 25.1 and 4.11 mV/V), and threshold voltage (VT = 0.56 and 0.58 V), respectively. These results indicate excellent electrostatic control and thermal stability. These outcomes were attributed to reduced lattice thermal conductivity, enhanced by alloy scattering and mass disorder, which suppresses phonon transport. The compatibility of Si₁₋ₓGeₓ with fabrication techniques such as mechanical alloying and spark plasma sintering supports its potential for integration into scalable, thermally aware nano-electronic systems. This study confirms that optimizing both geometric and material parameters enables high-performance, temperature-sensitive nanoscale FinFETs and broadens understanding of Si₁₋ₓGeₓ behaviour in elevated-temperature environments.