Study the effect of drain induced barrier lowering (DIBL) in CMOS device by using silvaco TCAD / Hashimah Hashim , Shafinaz Sobihana Shariffudin , Puteri Sarah Mohamad &Aad

A study of drain induced barrier lowering (DIBL) in CMOS device is presented. The study is based on the effect of DIBL due to short channel transistor. Three different values of drain voltage are biased in NMOS and PMOS device to see the role of this voltage on DIBL effects. From drain current, Id versus gate voltage, Vg curve, the value of DIBL (in milivolts) is obtained and analyzed to complete the analysis of DIBL in CMOS device. DIBL can be measured as the different in threshold voltage, Vt between a low and a high drain bias, Vd. Therefore, the value of DIBL is measured based on two different drain voltages. From Id versus Vd curve, it will show three different operation mode regions which are cut-off region, triode/linear region and saturation region. It also will show the maximum drain current, Id(max) and saturation slope of both NMOS and
PMOS device. All these simulation process are obtained by using SILVACO TCAD tools. Various electrical parameters are examined and plotted such as vertical and horizontal electrical field, potential, recombination rates, hole concentration and electron concentration. In this software, it can simulate MOSFET device by using ATHENA and ATLAS. The MOSFET structure and I-V characteristics also can be plotted using TONYPLOT. There are several fabrication process need to be changed to illustrate selected degradation that occur while scaling MOSFET e.g. implantation, oxide thickness and substrate doping concentration. The implantation temperature and the quantity of Hydrochloric Acid (HCL) in MOSFET device needs to be adjusted in order to reduce short channel effects i.e. drain induced barrier lowering, DIBL.