Design of low power high speed 1-bit full adder

Full adder is one of the important elements in microelectronics design. In view of the fact that 1 -bit full adder is the building block of most modules, therefore by improving 1-bit of full adder cell will lead to improvement of the whole system. In this paper, a 1 -bit full adder cell is implemented by using gate diffusion input (GDI) XOR and XNOR gates architecture technique. This technique is used because of its benefits in reducing the power consumption, delay and the size of digital circuits. The whole simulation for a 0.18 urn technology will be carried out by using Silvaco EDA tools.