High speed 4-bit flash ADC for pipeline ADC using 0.18μm CMOS technology: article

This paper describes a high speed 4-bit Flash Analog to Digital Converter (ADC) for Pipeline ADC. A high speed ADC is obtained by improving the comparator and the encoder design. In this paper, the conventional comparator is replaced with an open loop comparator and the non-ROM type encoder is used as the alternative for the conventional encoder. It is implemented in 0.18µm CMOS technology. Generally, the Silvaco Electronic Design Automation (EDA) Tools is used for drawing the schematics, do the simulations and designing the layout of the proposed Flash ADC. The simulation results include 1.8V analog input range and 24.2662 mW of power dissipation at maximum sampling frequency of 500MHz with the lowest propagation delay time of 539.61ps.