Implementation of quantization in MPEG-2 encoder using Xilinx FPGA technology

The aim of this project is to presents the design of quantization in MPEG-2 encoder for FPGA implementation using X1LINX FPGA technology. Quantization is the process that determines what information can be discarded without a significant loss. The purpose of this project is to study the quantization process used in N4PEG-2 video compression and implement it on FPGA by Xilinx. Very High Speed Hardware Description Language (VHDL) is used to program the behavioral logic design of quantization. The simulation of quantization process in Xilinx 1SE environment involves the 2D-DCT algorithm that is coded in VHDL. The pixel value is the applied to the testbench waveform to observe the output. The design is then implemented on two Xilinx FPGA technology; Spartan and Virtex model to study the speed of processing and resource utilization on several chips on each model.