Design of a RISC processor using VHDL

This paper describes the design and implementation of a Reduced Instruction Set Computer (RISC) processor using a hardware description language, VHDL. The design is based on simple Programmable Integrated Circuit (PIC) instruction set and standard 8-bit RISC processor architecture. RISC architecture has several advantages over other types of computer architecture such as pipelining, single cycle instruction execution time, and reduced instruction for flexibility. A processor or a Central Processing Unit (CPU) consists of two modules which are the datapath which performs the data-processing operations and the control unit which determines the sequence of those operations. Datapath generally consists of data register and function unit which carries out arithmetic and logic function. Control unit consists of program counter which decides what instruction is going to be next, instruction memory, and instruction decoder. When both modules have been designed, they are synthesized and simulated to test the design.