Automatic washing machine control using System Verilog HDL / Nurul Nafishah Safere

This research presents the design and implementation of an advanced automatic washing machine control system utilizing FPGA technology, specifically the Altera DE2-115 development board, programmed with System Verilog HDL. Traditional washing machine control systems rely on microcontrollers or microprocessors, which often face challenges related to processing speed, power consumption, and reconfigurability. To overcome these limitations, this study employs a Finite State Machine (FSM) architecture to efficiently manage the key operational stages, including load selection, door verification, water filling, washing, rinsing, spinning, and completion. The FSM was designed, simulated, and verified using ModelSim Edition 10.5b and Quartus Prime 20.1 Lite Edition to ensure precise state transitions and optimized process control. The system was successfully implemented on the Altera DE2-115 FPGA platform, demonstrating high-speed performance, real-time adaptability, and improved resource efficiency compared to traditional control methods. The experimental results confirm that FPGA-based designs provide superior flexibility, reduced execution time, and enhanced reliability, making them a promising alternative for embedded control applications in household appliances. Additionally, the modular nature of the design allows for future enhancements, such as IoT integration, machine learning-based cycle optimization, and improved fault detection mechanisms. This research contributes to the advancement of digital system design by showcasing how FPGA technology can revolutionize home automation and smart appliance control.