Design of folded cascode amplifier using 0.25µm technology driven bulk

This project presents the design, layout, simulation and comparison results of the Folded Cascode Amplifier with a different process variation. Emphasis has been placed on the comparison of the Folded Cascode performance. The Folded Cascode Amplifier structure were designed and laid out in TSMC 0.25µm CMOS technology. While the literature emphasizes is to design the Folded Cascode to meet the best performance. Simulated performance require that the Folded Cascode can obtain equivalent DC gain of 76dB, phase margin 48 degree, Gain Bandwidth 188MHz. power consumption 2.35mW under a 2.5V. The results show that the Folded Cascode has met the specification. Experimental testing needs to be carried out for the further evaluation.